Key Features

• Wide range of µP pods to emulate virtually all 8051 family members based on Intel and Dallas cores
• Real time transparent emulation up to 60 MHz
• HLL debug for C-51, PL/M-51 and ASM-51
• Up to 256K of overlay Program RAM with bank switching
• Up to 64K of overlay External Data RAM
• Memory display and edit while executing in real-time
• In-line symbolic assembler and disassembler
• Memory mapping on 256 byte boundaries
• Up to 256K of real-time hardware breakpoints
• 32K frames (80 bits wide) of execution Trace Buffer with time stamp
• Trace display during execution
• Pass-points to monitor internal RAM, variables and Registers while running
• Breakpoints on Register and internal RAM values
• Complex Events to trigger Breakpoints or Trace logic
• Two 16 bit Pass Counters
• 8 level hardware event Sequencer
• 8 channel user logic state analyzer
• External trigger input and outputs
• Performance analysis and histograms
• Coverage Analysis with source tagging and reports
• Windows 2000 / NT / 9x / ME / XP user interface
• Serial or parallel port interface to the host PC
• Remote debugging over TCP/IP network
• Virtual prototyping environment, VIPER

User Interface

Designed to work with IBM PC computers, the 8051 Windows user interface provides: multiple Source, Registers, Memory, Stack, Variables, Locals, Performance, Trace and other pop-up windows; source level debugger window for C-51 and PL/M-51 with automatic link to the Trace window; user defined variables in the Watch window.

Dual-Ported Memory

This unique feature allows instant viewing and modification of emulation memory (Program and Data) without stopping or slowing down the running 8051 application.

Complex Events

Through its Setup window, the 8051 emulator enables you to graphically program the three available complex events and to define how these events will be used for breakpointing and trace filtering. Each event is capable of comparing in real-time the address bus, data bus, and cycle type. This can be used, for example, to detect the writing of values between 44 and 55 to one or more specified locations in memory. Once a complex event is defined, it may be passed to one of the two available 16-bit counters to create a delayed breakpoint or trace trigger. With the use of the 8-level sequencer any combination of events and counters may be mixed to achieve a trigger based on a predetermined sequence of events.

Breakpoints

Breakpoints are used to stop user program execution while preserving the current program status. 8051 breakpoints can be triggered from a combination of:

• Addresses and address ranges;
• Complex Events;
• Register values and internal RAM;
• External input;
• Pass Counters;
• Sequencer;
• Trace full condition.

Trace Buffer

Trace buffer is a high speed RAM used to capture in real time all activity on the 8051 microprocessor bus and pins. A dedicated start/stop logic allows for filtering unwanted information from the trace buffer while executing. Trace will store up to 32 K samples (80-bit frames) comprised of the following:

• Address Bus;
• Data Bus;
• Control signals;
• I/O pins;
• Real Time Clock Stamp;
• User logic state inputs (8 bits).

The 8051 trace may be filtered before the information is stored with the use of complex events, and after the acquisition by choosing the filter menu. The trace is equipped with an internal counter to allow tracing to stop after a specified number of frames have been captured. This feature allows the trace to capture as much as 32K of small program fragments no matter how distant in time. The trace contents can be viewed during program execution without stopping or slowing down the 8051 microcontroller.

LAN Support and Remote Debugging

All Signum 8051 emulators support operation over a network. The IceServer option allows you to work with any ICE connected to a networked computer from any workstation on the network. You can also connect to any Chameleon debugging session using a standard telnet terminal session. This allows you to join a remote debugging session, for example, to take a peek at what is happening in the lab or at a test site.

ASIC 8051 Support

If you need to debug your 80C51 core based ROM-less 80C51 derivative or ASIC, but cannot physically remove the device from the system, POD51-ASIC is a perfect solution. This pod employs the 80C51 CPU core on the target PCB (or inside the ASIC device) in lieu of the conventional method of using the emulated CPU for in-circuit emulation. This effectively eliminates the need to remove the CPU/ASIC from the target board to perform non-intrusive real-time emulation! The pod provides all emulation objects, such as memory. Some of the POD51-ASIC features:

• Supports any ASIC with embedded 2.5-5V 8051 core
  • TDK 73S1121/1111/1112 at up to 66 MHz
  • Intel standard 12-clock core architecture
  • Atmel/Philips 6-clock core architecture
  • Dallas type core architecture
  • other architectures (please inquire)
• Works with Signum USP-51A emulator and Chameleon
• Reprogrammable (FPGA) and customizable
• Small, high-density (.5 mm pitch) connector
• Small and lightweight design (3.0 x 2.8 in.)

DCD Core Support

Our ICD8051-DCD in-circuit debugger enables you to perform complete real-time emulation of the digital Digital Core Design (DCD) series of 8051 cores without removing the processor from the system. The debugger comprises a Target Interface Unit (TIU) and Chameleon Debugger. With addition of a compiler/assembler, a complete development system is created which takes full advantage of the DCD On-Chip Debug logic (DoCD™) built into each DCD core. The ICD8051-DCD offers:

• Support at maximum clock speed for
  • all DCD 8051 cores
  • all CAST 8051 cores
  • other 8051 cores (please inquire)
• High-speed 3-pin debug interface to CPU
• Serial interface to your PC at up to 115 KBaud
• Small, lightweight design (1.5 x 3.5 in.)
• All benefits of DoCD™

Specifications

• Supported Microcontrollers
  Atmel and Atmel/TEMIC 89C51, 89C52, 89LV51, 89LV52, 89C1051, 89C2051, 89SC4051, 89S8252
  8xC51, 80C31X2, 80C32X2, 8x51X2, 8x52X2, 8xC54X2, 8x58X2, 8x51RA2, 8x51RB2, 8x51RC2, 8xC51RD2, 8xC51U2
  89C51CC01, 8xC5111/5112, 89C5101/5102, 89C5121, 89C5131
  89C51RD2, 89C51ID2, 89C51ED2
  Dallas Semiconductor 80C310, 80C320, 8xC520, 8xC530
  Infineon/Siemens 80C515, 80C535, 8xC515A, 8xC517A, 80C537, C501
  Intel 80C31, 80C32, 8xC51, 8xC52, 8xC54, 8xC58, 8xC51FA/FB/FC, 8xL52, 8xL54, 8xL58, 8xL51FA/FB/FC, 80C51GB
  OKI 80C31, 8xC51, 8xC154
  Philips/Signetics 80C31, 80C32, 8xC51, 8xC52, 8xCL31, 8xCL32, 8xCL51, 8xCL52, 8xC51FA, 8xC51FB, 8xC51FC, 8xC51RA+, 8xC51RB+, 8xC51RC+, 8xC51RD+, 8xCL410, 8xC451, 8xC524, 8X528, 8xC550, 8xC552, 8xC562, 8xC575, 8xC576, 8xCL580, 8xC652, 8xC654, 8xV748, 8xC749, 8xC750, 8xC751, 8xC752, 8xC781, 80C851;
  8xC51RA2, 8xC51RB2, 8xC51RC2, 8xC51RD2 (support with clock doubler)
  Silicon Systems K246, 73D2910, 73D2912, 73D2918
  TDK Semiconductor 73M2910L/2909, 73S1121/1111/1112
  Texas Instruments TUB3200, MSC1210
  Winbond 78C5x, 78E5x, 78L5x, 78LE5x
• Maximum emulation speed
  20 MHz, 40 MHz or 60 MHz
• Size
  260 mm wide, 260 mm deep, 64 mm high
• Max. Emulation Program Memory
  64 Kbytes standard, 256 Kbytes optional
• Max. Emulation External Data Memory
  64 Kbytes
• Program Memory mapping
  256 byte boundary
• Data Memory Mapping
  256 byte boundary
• Pass Counters
  Two, 16 bit each, with Stop/Reload control
• Trace buffer
  32 K deep, 80 bits wide with filtering control
• Real-Time Time Stamp
  32-bit, 100 ns resolution with Absolute, Relative and Delta modes
• Sequencer
  8 level hardware
• User probe
  8 channel logic input, 1 trigger input, 6 trigger outputs (Events, Pass Counters, Sequencer)
• Host interface
  Parallel (LPT1-LPT2)
  Serial RS-232C (COM1-COM4), 9600-115 KBaud
• File upload/download format
  Intel HEX, Intel AOMF, Archimedes, IAR, Franklin, Keil, Raisonance, Tasking and others

• 8051 In-Circuit Emulators